The present invention relates to a system on a chip (SoC) and a SoC control module, and more particularly, to a SoC control module for multiplexing pins of the SoC to internal modules and signals of the SoC.
SoCs can be provided in various types and sizes of packages. For example, one SoC design is provided in a package having 256 pins. In a typical arrangement, for each package pin, the SoC has a switch (such as a multiplexer) that allows any of four internal SoC signals to be connected to that pin to allow for external connection. Thus, each SoC pin may be multiplexed to support several functions and, in this conventional arrangement, this allows for a maximum of 4×256 (1024) signals to be routed between the package pins and the SoC circuit.
FIG. 1 illustrates a typical layout for such an arrangement, where the SoC has a series 100 of multiplexers 102a, 102b, 102c . . . 102m (collectively referred to 102). Each of the multiplexers 102 has a series of four inputs 104a to 104m (or collectively 104) for receipt of the SoC internal signals. Each multiplexer 102 also is provided with a respective output 106a to 106m, which outputs a signal received on one of the inputs 104 depending on the value on a the control line input 108a to 108m. Each of the control line inputs 108 is arranged to receive a 2-bit input signal that determines which of the four input signals is output. The multiplexers may also operate as demultiplexers for routing electrical signals from an external device through the pins to the components of the SoC. In such a case, the mux outputs 106a to 106m act as inputs of the demultiplexers, and the mux inputs 104a to 104m act as outputs of the demultiplexers.
However, design considerations may dictate a smaller package design, in which the number of package pins is reduced. For example, it is possible to have 32 pin/64 pin/144 pin/256 pin packages in a single product family. In such reduced-pin packages, only a reduced number of signals can be routed between the SoC circuit and the chip pins, which may cause significant design limitations. For instance, in a 32-pin package (and following the example of FIG. 1 where each multiplexer has four inputs for routing signals to/from the SoC components), a maximum of 4×32 (128) SoC signals can be connected with the package pins, and then other i/o cells of the SoC are unused since they cannot be connected to package pins. Further, each unused pad and its associated i/o cell, which may incorporate numerous electronic devices such as level shifters, digital drivers and electro-static discharge (ESD) protective circuitry, remains energized and consumes unnecessary electrical power.
Thus, existing techniques are less than optimal because of the restrictions discussed above. Accordingly, it would be advantageous to be able to more readily connect more SoC signals to package pins and overcome the limitations discussed above.